TRANSISTORS

The field effect transistor (FET):

The field effect transistor consists of a piece of n-type semiconductor, into which two smaller pieces of a p-type semiconductor are embedded. These smaller pieces are called the GATE (G), and are electrically connected so that they are always at the same potential (this connection is not shown in the diagram on the left). The gate forms a channel through which current can pass, from the DRAIN (D), to the SOURCE (S) (). Wires are attached to the gate, drain, and source. This design applies to what is called an "n-channel FET". If the gate is made up on an n-type semiconductor, and the channel of a p-type semiconductor, the device is called a "p-channel FET" - the operating principle is the same.

If we connect the transistor to a variable DC power source, and complete the circuit as shown above (the diagram on the right shows a more conventional way of describing the circuit), the gate voltage will be zero, but there will be a positive voltage, V_DS, between the drain and the source at all points within the channel. This reverse-biases the p-n junctions between the n-channel and the gate (), creating depletion zones around the gate, resulting in a narrowing of the n-channel. No current can flow from the channel through the gates, but current (the DRAIN CURRENT, I_D) can flow from drain to source.

If we increase the applied voltage, VDS will increase, and this will widen the depletion zones, consequently narrowing the channel. The current flowing through the channel will vary with VDS as shown in the graph on the right. The drain current-drain (ID) to drain-source voltage (VDS) curve () van be divided into three regions:

• An ohmic region, where the current obeys Ohm's law: I_D = R/V_DSR_DS where R_DS is the resistance of the n-channel.
• A region where the current assumes a constant value I_DSS, due to a simultaneous increase in resistance as the channel narrows in concert with increasing reverse-bias and consequent further narrowing of the n-channel, and,
• a breakdown region where current rises sharply with increasing values of V_DS. Operating in this region will ruin the transistor!

It is important to realize that I_DSS, the maximum operating current, is only obtained when the gate and the source have zero potential difference between them (V_GS = 0). The value of V_DS at the point where I_D achieves the value I_DSS is called the PINCH-OFF VOLTAGE, V_p.

If we now introduce a negative gate to source voltage, V_GS, the reverse-bias between the gate and n-channel will be increased, increasing the width of the depletion zone. In other words, the value of the V_GScontrols the width of the n-channel: the greater V_GS, the more narrow the channel (see diagram above):

This has for effect a reduction in the maximum value of the drain current that can be obtained for given values of V_DS, as shown in the figure above, right) (). We see that above the pinch-off voltage (that is, in the flat region of the curve) the drain current is controlled by the gate to source voltage V_GS Note the following:

• V_DS is a positive voltage, while V_GS is negative.
• No appreciable current flows from the gate to the n-channel or vice-versa, since the reverse-biased p-n junction offers a very high resistance.
• When V_GS = -V_p, I_D @ 0, that is, no current flows through the transistor. That value of V_GS is labelled V_GS(OFF).

Manufacturers normally supply a variety of transistors, and make data available for each model. Thus, for an n-channel FET, V_GS(OFF) and I_DSS would be known.

The relationship between I_D, I_DSS, V_GD and V_GS(OFF) is given by Shockley's equation: